Limits. Symbol. Parameter. Conditions. −40°C. +25°C. +85°C. Units. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. IL. Quiescent Device. VDD = V. Data sheet acquired from Harris Semiconductor. SCHSC – Revised September The CDUB types are supplied in lead hermetic dual-in- line. Order Number CD C National Semiconductor Corporation . This datasheet has been downloaded from: Datasheets for.
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Connect pin 4, which serves as Q output of the latch to DIO8. During the hold phase of the latch, i. You should take a total of three catasheet, one each, corresponding to each inverter output. You may find the diagram shown below in figure 13 helpful. Created using Sphinx 1.
Each datasheey shares a common gate pins 6,3, For the complete circuit you will need fd CD chips. Construct the circuit shown in figure Remember to ground the CH – terminals.
A steady high should appear. Application of CMOS logic. Describe the differences between the screenshots other than that they are inverted. You may find the diagram shown below in figure 13 helpful. Remove the capacitor from the previous step.
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The two transmission gates work in tandem to cd datasheet the D-latch. Datasheeh, the input to the first inverter is close to the voltage at node C.
Construct 3 inverters using a CD by making the following connections: Your output should look similar to figure Attach screen shots for different VDD. Ids-Vds curves for multiple gate-to-source voltages Vgsfrom which we can observe linear and saturation operation regions. Note each transistor has four terminals: The output is pin 12,13, or 5.
Application of Cd datasheet logic. Enter search terms or a module, class or function name.
Now insert two inverter chain you built earlier and retained from the first exercise to the circuit you have just built. Created using Sphinx 1.
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Navigation index next previous elec 1. Determine the VPP and dc offset setting required for function generator. You should see that DIO8 is also low. This is because CMOS logic requires a voltage input of 0-Vdd and the function generator always provides a waveform with a dc component of 0 V.
Navigation dd4007 next previous elec 1. Cd407 the output voltage of the second inverter and the voltage across the capacitor with the scope. Draw a pin-level wiring diagram of a CMOS inverter. Quick search Enter search terms or a module, class or function name. What to do in the lab report Attach screen shots for working frequencies, and for too high frequencies such that transitions between 0 and VDD are not complete.
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For example, a single CD can be used to make datashwet chain of 3 inverters, an inverter plus two transmission gates, or a complex logic gate. What to do in the lab report Show 1 screenshot. Try increasing the frequency and see at what frequency the inverter has trouble completing high to low and low to high transitions. You will see how the voltage transfer curve changes with VDD. Table Of Contents 7. It should look as shown in Figure 7.
Show 3 screen shots of inverter outputs. Clean up Previous topic 7. You should see that DIO8 is also low. For example, consider 22,5,7 ; 1,3, Make a pin-level wiring diagram for a transmission gate using a CD For example, consider 22,5,7 ; 1,3, Describe the differences between the screenshots other than that they are inverted.
Observe the output on DIO8.
Schematic of D latch.